In order to read out an image captured by a CMOS imager, readout circuitry is generally co-integrated on the same chip as the image sensor itself, thus creating a camera-on-chip which is highly suitable for mobile applications, such as mobile telephones, personal digital assistants (PDAs), and the like. An important component of the readout circuitry of a CMOS imager is the analog-to-digital converter (ADC) to convert the output of the imaging array into the digital domain. Such conversion can be implemented with a single ADC that converts the output signal of the complete imaging array into the digital domain. The advantage of this single-channel solution is that it ensures a uniform A/D conversion for the whole imaging array and, as only a single ADC is used, it uses relatively little chip area. However, such an ADC must operate at the speed dictated by the application and therefore implementing an on-chip low-power ADC for high speed applications can be a challenge. Furthermore, as the necessary bandwidth increases due to higher imager resolutions, it becomes increasingly difficult to design a single ADC with a sufficiently high signal-to-noise ratio.
At least some of these difficulties can be overcome by incorporating either a multi-channel ADC or several ADCs in parallel. For example, a so-called massive-parallel ADC could be employed whereby one ADC channel is provided for each column of the imaging array of a CMOS imager.
There are many different types of ADC known in the art. One of the simplest configurations is called the digital ramp ADC, wherein the output of a free running binary counter is connected to the input of a digital-to-analog converter (DAC). As the counter counts up with each clock pulse, the DAC outputs a slightly higher voltage. This voltage is compared against the input voltage by a comparator. If the input voltage is greater than the DAC output, the counter will continue counting normally. However, eventually the DAC output will exceed the input voltage, at which point the ADC circuit output is updated using the binary count output by the counter, and the counter is reset ready for the next input voltage, i.e. the DAC output ramps up to whatever level the analog input signal is at and the binary number corresponding to that level is output, before the counter is reset and the process starts again for the next analog input signal. However, the variations in sample time with this type of ADC make it unsuitable for some applications. Furthermore, the counter has to keep counting from zero for each analog input signal. Therefore sampling of the analog signal is relatively slow.
One way of addressing the above-mentioned disadvantages of the digital ramp ADC is to use a so-called successive approximation ADC. Referring to FIG. 1 of the drawings, the principal components of a successive approximation ADC are a comparator 10 with inputs for receiving the analog input signal Vin and the output of a DAC 12, and a digital controller 14. The only change in this design relative to the digital ramp ADC is a special counter circuit known as a “successive approximation register”. Instead of counting up in a binary sequence, this register counts by trying all values of bits starting with the most significant bit and finishing at the least significant bit. Throughout the count process, the register monitors the comparator's output to see if the binary count is less than or greater than the analog signal input, adjusting the bit values accordingly. In this case, the DAC 12 is controlled by a digital block 14 that tries to approximate the input voltage as well as possible based on the previous comparator output. This well-known architecture is relatively power efficient and, because the DAC 12 output converges on the analog input signal in much larger steps than with the zero-to-full count sequence of the regular counter of the digital ramp ADC, sampling of the analog signal is significantly faster. However, the DAC output depends on the input signal and thus, a separate DAC is needed for every ADC channel. In a massive-parallel system, this is unattractive since all the DACs have to be matched to achieve a uniform system response, and this is relatively difficult.
The use of a DAC can be avoided altogether by substituting an analog ramping circuit and a digital counter with precise timing, as in a single slope ADC. Referring to FIG. 2, there is illustrated a known single-slope massive parallel ADC architecture comprising, for each column of an imaging array, a comparator 10a, b, c with inputs for receiving a respective analog input signal Vin and the output of an op-amp circuit or ramp generator 16. The output of each comparator 10 is fed to a respective latch and digital control module 18a, b, c for generating respective digital outputs. The output of a digital counter 20 is connected to each latch and digital control module 18.
The ramp generator 16 generates a sawtooth waveform which is then compared with an analog input Vin by a respective comparator 10. The time it takes for the sawtooth waveform to exceed the input signal voltage is measured by means of the digital counter 20 clocked with a precise-frequency square wave (usually from a crystal oscillator). When the input voltage Vin is greater than the ramp generator output, the ramp generator 16 is allowed to charge a capacitor thereof in a linear fashion. Meanwhile, the counter 20 is counting up at a rate fixed by the precision clock frequency. When the capacitor reaches the maximum input voltage level (corresponding to the maximum counter value of block 20), a final output is generated, the capacitor is discharged back to zero, in response to which the counter 20 is cleared and the ramp generator 16 is allowed to ramp up the voltage once again.
The architecture described above enables the use of a large number parallel channels by using a central ramp generator 16 and digital counter 20, which can be connected to a large number of comparators 10 and digital latches 18. The advantage of this approach is that the amount of circuitry required for each ADC channel is relatively low, primarily only a comparator 10 and a latch 18. This is essential for application in CMOS imagers, where every ADC channel has to fit within a pixel pitch width. Moreover, as the only analog component per channel is a comparator, it is relatively easy to ensure a uniform transfer function for all ADC channels. In theory, only the comparator offset can cause non-uniformities, and this can be reduced using dynamic offset cancellation techniques. It is for these reasons, among others, that the so-called column-parallel ADC architectures mostly use single-slope ADCs. However, the main disadvantage of the single-slope architecture is that it is relatively slow which results in relatively high power consumption. For each ADC channel, an n-bit A/D conversion takes 2n comparator decisions. A detailed analysis of comparator operation has demonstrated that it is most efficient to implement it with a preamp and regenerative latch, where the regenerative latch consumes the most power. In a latch, the power consumption is proportional to the number of comparator decisions per unit time. More generally, a conventional massive-parallel ADC will contain a large number of comparators, which will consume most of the power required by the ADC. Thus, reducing the comparator power consumption is the key to reducing the ADC power consumption. In other words, it is advantageous to minimize the number of comparator decisions in order to minimize power consumption.
Although the successive approximation ADC described above can perform an A/D conversion of n bits using only n comparator decisions, so that it can be made more power efficient than the known single-slope architectures, the requirement for a DAC for each ADC channel makes it unattractive for use in a massive-parallel system because, as explained above, all of the DACs have to be matched to achieve a uniform system response, and this is difficult.